This paper presents an efficient CMOS rectifier with dual dynamic gate/body self-biasing network design to improve power conversion efficiency (PCE) and sensitivity. The proposed rectifier is designed using a 180 nm CMOS process and occupies a silicon area of 102 μ m x 78 μ m. At 920 MHz, it achieves a high PCE of 78.5% at an input power ( PIN ) of -18.9 dBm. It demonstrates a dynamic range (DR) of 26.1 dB and a sensitivity of −18.4 dBm, with an output of 1 V across a 100 k Ω load. The proposed rectifier achieves a 29% increase in DR and a 27% improvement in sensitivity compared to the conventional rectifier. Moreover, the proposed rectifier architecture outperforms prior single-stage rectifiers in terms of PCE, sensitivity, and dynamic range.