This paper presents the realization of a CMOS-grounded positive and negative capacitance multiplier (CM) with an extremely high multiplication factor. The proposed CM is primarily constructed by cascading configurable modified second-generation current conveyors (M-CCII) that offer flexible configuration during CM integration. The functionality of the proposed design is validated using Cadence with the 180 nm TSMC CMOS process technology. The design is powered by a 1.8 V supply voltage and consumes 250 W of power. Simulation results indicate that the multiplication factor ( ) is 50,625 with a maximum relative error of 5% and the proposed CM occupies a silicon area of 0.026 mm . Furthermore, the influence of non-ideal factors is analyzed to assess the parasitic effects on performance. The pre- and post-layout simulation results are closely matched and consistent. Moreover, statistical analyses using Monte Carlo (MC) and process-voltage-temperature (PVT) variations are conducted to verify reliable performance in the manufacturing process going forward. Furthermore, as evidenced by the comparative table and overall performance, the figures of merit (FOMs) indicate that this work outperforms previous designs. A low-pass filter with a corner frequency of 6.4 Hz, designed using the proposed CM, is implemented to suppress power line interference during the acquisition of the photoplethysmography (PPG) signal. In the end, to verify the reconfigurability and reusability of the proposed design, commercial ICs such as the LMC6482, ALD11007, and ALD11006 are employed in experimental setups.