This paper aims to present an automated design algorithm for a robust analog circuit approach. The proposed algorithm bases on the simulation annealing concept to obtain the dimensions of transistors and biasing currents for certain specifications. This algorithm consists of four stages; gm/ID estimation, chart density extraction, regressing model, and refine stage. The proposed algorithm provides a computer-aided design tool for reducing the time spent through the design cycle by a scripting language. Moreover, it is compared with an advanced compact MOSFET model. To verify the proposed algorithm, three designs of the NMOS differential pair amplifier with different required specifications are used to attain inferior errors in the most significant specifications. The circuit is simulated by IBM 0.13 µm CMOS process with a single power supply 1.5-V.