This paper presents a software program for automatic circuit and chip synthesis. The proposed program is suitable for automatic design and Layout generation for the repeated modules circuits. The program outcome is a netlist file compatible with spice for simulation. The proposed program can be employed for automatic full custom chip layout design. The developed system is started form the low level circuit hierarchy level (bottom to post). The matrix-ROM system is an example of repeated cells circuit (0/MOST & one/no MOST). An audio signal can be stored in the ROM by processing it to digital form (1's & 0's) with signal conditioning. The netlist file is generated by using the proposed program and simulated. The simulation result is verified with the original circuit response. The proposed tool then generates a silicon chip layout file from the audio binary signal file automatically.