This paper presents a novel input offset cancellation technique dedicated for analog building blocks. This technique provides an injected current to the analog input signal that is a function of the offset. The proposed technique provides a suitable method to the post-package offset cancellation. Unlike, other convention techniques, the proposed technique avoids the potentially stability issue, consumes a low silicon area, low power consumption, and temperature independent. The input offset cancellation circuit is attached to the input stage of the differential input single output (DISO) amplifier to revoke undesired DC, offset voltage (Vos, out), based on trimming current (ITrim). DISO amplifier with input offset cancellation circuit is simulated and comprehend a DC gain of 78 dB, a unity-gain frequency (GBW) of 58 MHz associated with a phase margin of 670. Moreover, the total consumption power is 0.72 mW. The statistical analysis with practical different coefficients provided from foundry demonstrates offset voltage less than 200 μν. The circuit is simulated in IBM 0.13μm CMOS technology with a single power supply 1.5-V.