This paper presents a novel technique for an automated design to produce a constant transconductance (gm). This constant gm is valid over the entire common-mode input range for input stage of Low Voltage (LV) operational transconductance amplifier (OTA) based on DC level shifter. The issue lies at the input sage so, this automated design technique is created to rail-to-rail input stage of OTA. The key parameter is the bias current in DC level shifter (Ish). The proposed technique is responsible for finding the optimal Ish to obtain minimum variation on the gm of the OTA input stage. This technique is based on a script written on Linux, operating system, to be connected to the BSIM MOST model and netlist of the desired topology. Utility of the physics-based gm/ID characteristics, this technique is more suitable for short channel transistors in submicron processes. This work allows the design problem to be cast as a program. So, it offers an efficient, reliable, and fast way to implement high-performance of analog integrated circuits. The results demonstrate that gm variation can be restricted within ±1.25 %. The circuit is simulated in IBM 0.13μ CMOS technology with a single power supply 1.5-V.