New active capacitance multiplier for low cutoff frequency filter design

This paper presents a new topology for an active capacitance multiplier. This circuit affords a technique to implement a high capacitance value using a small on-chip capacitor. The proposed capacitance multiplier is build up by cascading current multiplier cells (CMC). The circuit is preferred for low power low voltage applications since it is based on CMOS inverters and op-amps only. The capacitance multiplier is employed in the design of a second-order LPF with a programmable cutoff frequency. The cutoff frequency can be as low as 65 Hz using an on-chip capacitor of 1pF only. The static power dissipation is equal to 3 mW. Some practical considerations are discussed. The circuit is simulated using CMOS 0.13 mu m process. Simulation results show good agreement with the analytical calculations.