CMOS buffer amplifier for wide bandwidth applications

This paper describes a new configuration of a CNIOS buffer circuit. The new buffer is based on a Flipped Voltage Follower (FVF) with feedback in order to enhance the transconductance of the buffer as well as linearity. The proposed cell can be used as a very high bandwidth buffer to drive high capacitive loads. The employed feedback enhances the overall transconductance while minimizing the loading effect. The circuit is designed and simulated by using 0.13 mu m CMOS process. The proposed buffer is compared with a conventional voltage-follower and flipped-voltage-follower for a capacitive load up to 30 pF. Simulation results show a bandwidth of 145 MHz for a capacitive load of 30 pF. The power consumption is 2.4 mw for 1.5 V power supply.