A highly parallel SAD architecture for motion estimation in HEVC encoder

Faculty Engineering Year: 2014
Type of Publication: ZU Hosted Pages: 4
Authors:
Ahmed Medhat Mohamed Monir Abdulsalam
Journal: Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on Volume:
Keywords : , highly parallel , architecture , motion estimation , HEVC    
Abstract:
The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD resolutions incre
    
     
 
       

Author Related Publications

  • Ahmed Medhat Mohamed Monir Abdulsalam, "Fast center search algorithm with hardware implementation for motion estimation in HEVC encoder", Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on, 2014 More

Department Related Publications

  • Mohammed Ayesh Muhammad Hanafi, "Compressed sensing for reliable body area propagation with efficient signal reconstruction", IEEE, 2018 More
  • Saleh Ibrahiem Saied Saleh, "Rate Splitting Multiple Access Scheme for Cognitive Radio Network", The Egyptian International Journal of Engineering Sciences and Technology, 2021 More
  • Saleh Ibrahiem Saied Saleh, "Performance Evaluation of 5G Modulation Techniques", Springer US, 2021 More
  • Nabila Alsawy Elsayed Elsawy, "Mode Skipping for Screen Content Coding Based On Neural Network Classifier", Springer, 2021 More
  • Nabila Alsawy Elsayed Elsawy, "Efficient Coding Unit Classifier for HEVC Screen Content Coding Based on Machine Learning", Springer, 2022 More
Tweet