A highly parallel SAD architecture for motion estimation in HEVC encoder

Faculty Engineering Year: 2014
Type of Publication: ZU Hosted Pages: 4
Authors:
Ahmed Medhat Mohamed Monir Abdulsalam
Journal: Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2014 IEEE Asia Pacific Conference on Volume:
Keywords : , highly parallel , architecture , motion estimation , HEVC    
Abstract:
The high computational cost of the motion estimation module in the new HEVC standard raises the need for efficient hardware architectures that can meet the real-time processing constraint. In addition, targeting HD and UHD resolutions incre
    
     
 
       

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