| Abstract: |
Recent efforts in the design of integrated circuits for RP communicationtransceivers have focused on maximizing the dynamic-range of modem wirelesscommunication systems, medical equipment, hearing aids, disk drives, and soon, as well as adaptability to multiple RP communication standards.The demand for wide-bandwidth and variable gain for telecommunicationapplications requires a Variable Gain Amplifier (VGA) in the baseband. TheVGA receives an input signal with wide dynamic-range and continuously triesto maintain the output signal at a constant level through an Automatic GainControl (AGC) loop. The output of the VGA is applied to the Analog-to-DigitalConverter (ADC). The signal level to the ADC should be kept at its maximumlevel to achieve optimum SNR. These requirements of wide bandwidth andinput dynamic-range for the VGA should be achieved at reasonable powerdissipation.Our thesis describes a novel circuit topology for a Programmable VariableGain Amplifier (PVGA) as well as output buffer. The PVGA is composed of twovariable gain amplifier stages and an output buffer. It can achieve 400 MHzbandwidth with 62 dB dynamic-range. Power reduction is developed for thevariable gain amplifier stages and output buffer. The PVGA circuit is designedand simulated in a 0.13 urn IBM-CMOS process. The simulation results show aminimum bandwidth of 420 MHz at gain of 50 dB. Such wide bandwidth allowsour proposed PVGA to be used in multi-standard protocols. The variable gainamplifier achieves a wide dynamic-range of 62 dB. The circuit has a THD of -40dB at peak-to-peak differential output voltage of 700 m V and frequency 400MHz. Moreover; the proposed circuit reports a good noise performance; the
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