Performance analysis of input-buffered ATM switch

A way to resolve output port contention is to place a buffer in each input port, and to select only one cell for each output port among the cells destined for that output port before transmitting the cell. This type of switch is called the input –buffered switch .An arbiter decides which cells should be chosen and which cells should be rejected .This decision can be based on cell priority or timestamp ,or be random.• A well – known problem in a pure input – buffered switch with first –in- first-out(FIFO) Input buffers is the head of line (HOL)blocking problem .This happens when cells are prevented from reaching a free output because of other cells that are ahead of it in the buffer and cannot be transmitted over the switch fabric.Due to the HOL blocking, the throughput of the input buffered switch is at most 58.6%for random uniform traffic.• To alleviate the HOL blocking in input-buffered switches is for every input to provide a single and separate FIFO for each output. Such a FIFO is called a virtual output queue )VOQ(• The PIM scheme uses random selection to solve the contention in inputs and outputs. Input cells are first queued in VOQs. Each iteration consists of three steps. All inputs and outputs are initially unmatched, and only those inputs and outputs that are not matched at the end of an iteration will be eligible to participate in the next matching iteration.• the maximum throughput of an ATM switch with one iteration PIM scheduling converges to 0.63 when the switch size grows.To improve the throughput, the original PIM algorithm performs extra iterations (during the same time slot) so that more inputs are matched in each iteration. To obtain 100% throughput, the iterations should be repeated until all the inputs are matched. It has been shown that, to get 100% throughput an expected number of iterations is required.• A new scheme is proposed in the present work to achieve 100% throughput of a VOQ-based ATM switch without doing iterations except the first one. The proposed scheme depends on a parallel matching algorithm that runs for only one iteration and then passes the excessive grants from inputs receiving multiple grants (multi-granted inputs) to the requesting inputs that have not received any grant (ungranted inputs). Thus all the inputs are matched within only one iteration. Naturally, this is accomplished on the expense of adding some complexity to the switch circuitry.7-2) Future WorkFuture work can be directed in one of the following directions:• The analysis presented in this thesis is assuming that the traffic is uniformly distributed on the input ports .Then ,we can improve this work by assuming that the traffic is burst distribution.• Another direction is the elaboration of the analytical techniques, by finding suitable values for the throughput and delay parameters for the new scheme.